1. Field of the Invention
The present invention relates to a power management circuit and gate pulse modulation circuit thereof, and more particularly, to a power management circuit and gate pulse modulation circuit thereof capable of increasing power conversion efficiency.
2. Description of the Prior Art
In general, each of sub-pixels in a liquid crystal display (LCD) device includes a thin film transistor (TFT) and a liquid crystal capacitor. Since there is a parasitic capacitor appears between a gate and a source of the TFT, electric charges stored in the liquid crystal capacitor are subject to the coupling effect of the parasitic capacitor during a discharging period, which affects image data intended to display.
For example, please refer to FIG. 1, which is a schematic diagram of a sub-pixel 10 in a LCD device in the prior art. As shown in FIG. 1, the sub-pixel 10 includes a TFT 100 and a liquid crystal capacitor 102, wherein a parasitic capacitor CGD is between the gate and the source of the TFT 100. A timing controller of the LCD device performs timing control, such that a gate driving voltage of a scan line GL can turn on the TFT 100 during a gate high-level voltage VGH, and thus a data line SL can charge the liquid crystal capacitor 102 to a desirable voltage level to display image data. However, when the gate driving voltage of the scan line GL switches to a gate low-level voltage VGL to turn off the TFT 100, since the parasitic capacitor CGD is between the gate and the source of the TFT 100, voltage switching of the gate of the TFT 100 (i.e. switching from the gate high-level voltage VGH to the gate low-level voltage VGL) may couple to the source of the TFT 100 via the parasitic capacitor CGD, and affect a voltage level stored in the liquid crystal capacitor 102, so as to affect image data intended to display.
In such a situation, please refer to FIG. 2A, which is a schematic diagram of reducing the coupling effect of the parasitic capacitor CGD shown in FIG. 1 in the prior art. As shown in FIG. 2A, compared with directly switching the scan line GL from the gate high-level voltage VGH to the gate low-level voltage VGL (as shown in the left part), in order to reduce the coupling effect of the parasitic capacitor CGD, during this conventional process of switching the scan line GL from the gate high-level voltage VGH to the gate low-level voltage VGL, the gate high-level voltage VGH is reduced to 0V with a discharging slope first, and then to the gate low-level voltage VGL (as shown in right part). As a result, instantaneous voltage variation across two terminals of the parasitic capacitor CGD is reduced, which effectively reduce the coupling effects from the gate of the TFT 100 to the source of the TFT 100.
In detail, please refer to FIG. 2B, which is a block diagram of a gate pulse modulation circuit 20 for realizing functions shown in the left part of FIG. 2A. As shown in FIG. 2B, the gate pulse modulation circuit 20 includes pins 200-206. the pin 200 receives a switch control signal VFLK (can be provided by the timing controller), the pin 202 receives the gate high-level voltage VGH, the pin 204 is coupled to a ground (0V) via a discharging resistor RE, and the pin 206 outputs a gate control signal VGHM for gates of TFTs of all sub-pixels in LCD device. An equivalent aggregate parasitic capacitor C_VGHM can be equivalent to a sum of parasitic capacitors between the gates and the sources of the TFTs of the all sub-pixels, and thus the gate control signal VGHM may simultaneously charge/discharge the equivalent aggregate parasitic capacitor C_VGHM.
In respect to the specific operations of the gate pulse modulation circuit 20, during a gate charging period, the switch control signal VFLK is at a high voltage level, so that the gate control signal VGHM is the gate high-level voltage VGH while charging the equivalent aggregate parasitic capacitor C_VGHM to the gate high-level voltage VGH. In addition, during a gate discharging period, the switch control signal VFLK is at a low voltage level, so that the gate control signal VGHM equals a voltage of the equivalent aggregate parasitic capacitor C_VGHM in the beginning, and the gate control signal VGHM discharges to 0V via the discharging resistor RE.
However, the gate pulse modulation circuit 20 in the prior art discharges the charges stored in the equivalent aggregate parasitic capacitor C_VGHM to ground during the gate discharging period, and thus the stored charges is not utilized efficiently.